The present invention relates to a graphic processor for rendering computer graphics elements.
In recent years, the computer graphics (CG) technology has seen a remarkable progress. Typical applications of computer graphics include CAD, CAE, video games, etc. Recently, computer graphics has also been used for displaying map information such as in car navigation systems.
Computer graphics requires a graphics command for performing a graphic operation and coordinate data of an element to be rendered. A texture mapping technique of applying a texture on an element requires texture data representing the texture to be applied on the object. In recent years, along with the increase in the amount of data which can be processed, there is a demand for a finer graphic operation, whereby the amount of rendering data required has been ever increasing. While computer graphics also requires a frame buffer for storing image data of a display screen, the size of the display screen has also been increasing. As a result, a contemporary graphic processor requires a work memory with a huge storage capacity.
Conventionally, a data memory to be the work area for processing the rendering data and a frame memory to be the rendering area for storing display data are configured separately. Recently, a unified memory architecture (UMA) has been proposed in the art, where the work area and the rendering area are configured in a single memory. In the unified memory architecture, the relationship between the graphic processor and the memory is uniquely determined, thereby simplifying the system configuration and significantly reducing the cost.
FIG. 10 is a block diagram illustrating a configuration of a conventional graphic processor. Referring to FIG. 10, a graphic processor 200 receives, via an external bus 201, a graphics command which is generated between a CPU 202 and a memory 203. The received graphics command is supplied from a CPU interface 211 to a FIFO memory 215 via a first data bus 213. The graphics command received by the FIFO memory 215 is decoded by graphics command decoding means 216, and rendering means 218 performs the graphic operation according to the decoding result. Display data obtained by the graphic operation is supplied from a memory interface 212 to a work memory 204 via a second data bus 214. The display data stored in the work memory 204 is supplied to display means 219 via the second data bus 214 and displayed on a display device 205.
Thus, while an externally-input graphics command is supplied to the FIFO memory 215 via the first data bus 213, the other data is transferred between the CPU interface 211 and the memory interface 212 via the second data bus 214.
Problems to be Solved
Possible approaches to increase the data transfer rate for the purpose of improving the rendering performance include, for example, to improve the operating speed (clock rate) or to increase the bus width of a data bus. However, an increase in the operating speed creates other problems such as an increase in the power consumption. Therefore, in many cases, the data bus width is increased. However, since the conventional graphic processor as described above requires at least two data buses, the increase in the bus width may lead to a significant increase in cost in a case where the graphic processor is implemented in an LSI.
Another possible approach is to share a data bus. In such a case, however, a plurality of types of data flow along the single data bus, whereby data transfer operations may contend with one another, leading to other problems, e.g., it may be difficult to ensure a desirable graphics command supply rate, or the displayed image may be intermitted. A possible solution to such problems is, for example, to substantially increase the storage capacity of an internal memory. However, such a solution also leads to a significant increase in cost.
A graphics command is typically variable-length data, not fixed-length data. This is because coastlines, residential blocks, etc., used in map rendering as in car navigation systems, for example, require element data consisting of a series of many coordinate points which cannot be represented by simple triangles and/or rectangles.
For example, a road, or the like, is represented by a series of straight lines as illustrated in FIG. 11A, and a graphics command for rendering such a series of straight lines contains a plurality of coordinate points constituting the series of straight lines as illustrated in FIG. 11B. A residential block, or the like, is represented by a polygon as illustrated in FIG. 12A, and a graphics command for rendering such a polygon contains a plurality of coordinate points constituting the boundary line thereof as illustrated in FIG. 12B.
Where the inside of the element as illustrated in FIG. 12A is filled, in order to quickly complete a graphic operation, the filling operation cannot be performed until the boundary line has been drawn. Accordingly, it is indispensable to quickly complete drawing the boundary line. Therefore, for animation display with scrolling at a time interval of, for example, {fraction (1/30)} sec or {fraction (1/60)} sec, it is necessary to supply sufficient coordinate data required for the graphic operation. The operation of filling the inside of an element can be performed according to, for example, the algorism disclosed in “Jissen Computer Graphics”, Nikkan Kogyo, pp. 100-102.
In order to reliably supply a graphics command containing such variable-length data with the above-described conventional example, it is necessary for the CPU to control the FIFO memory storing the graphics command of the graphic processor at a predetermined time interval. In such a case, however, a substantial load is imposed on the CPU, and the load is particularly significant when processing a graphics command with a great data length. However, since the CPU performs OS operations for the graphic processing system as a whole, such a load on the CPU may deteriorate the overall performance or response speed of the system. While improving the performance of the CPU is of course a possible solution, it will increase the system cost. A possible approach to reduce the load on the CPU is to increase the storage capacity of the FIFO, but this also lead to an increase in cost.